1. Field of the Invention
The present invention relates to an image reading device that can suppress image-level fluctuation, an image reading method, and an image forming apparatus that includes the image reading device, such as a digital copier, a facsimile machine, and a digital multifunction product.
2. Description of the Related Art
With the demand for high image quality and high running speeds, more and more image reading devices with high pixel density and high running speeds are being used. In a conventional digital copier, signal processing to convert image data that is read by a photoelectric conversion element into a digital image signal is performed, for example, in the following manner.
FIG. 11 is a block diagram of signal processing circuits used in a conventional image reading device. A clock signal coming from an oscillator 101 is converted into a frequency-modulated clock signal by an SSCG circuit 102. The frequency-modulated clock signal is converted into a multiplexed signal by a PLL circuit 103. The multiplexed signal is converted into a CCD driving signal and a signal-processing IC driving signal by a timing generating circuit 104.
A CCD 105, which converts light reflected from an original into an electric signal, is driven according to the frequency-modulated clock received from the timing generating circuit 104 and outputs an analog image signal to an AFE (signal processing IC) 107 via an emitter follower (EF) circuit 106. The AFE 107 includes a clamp circuit 108, a sample/hold (S/H) circuit 109, a programmable gain amplifier (PGA) 110, and an AD converter (ADC) 111.
The AC-coupled analog image signal is clamped to an internal reference potential of the AFE 107 by the clamp circuit 108. The clamped analog image signal is subjected to sampling using a sample pulse, which is a signal-processing IC driving signal, by the S/H circuit 109 so as to maintain its level and thus a continuous analog image signal is generated. The continuous analog image signal is amplified by a predetermined percentage by the PGA 110. The amplified analog image signal is converted into digital data by the ADC 111.
In general, as the pixel density increases or the image reading speed increases, the frequency of the clock according to which the CCD 105 that reads images is driven or the frequency of the clock according to which the AFE 107, which performs various signal processing on the analog image signal received from the CCD 105, is driven increases. The increase in the frequency of the clock increases undesired radiation of electromagnetic waves. To solve the problem, downstream of the oscillator that is used to generate the clock signal, a unit that performs frequency modulation is added (the use of an oscillator that has a frequency modulation function is allowable) to decrease the intensity of the undesired radiation corresponding to the peak of the frequency. This technology is called, herein, “SSCG”.
FIG. 12 is a characteristic diagram of a conventional SSCG characteristic. The SSCG is an abbreviation of “spread spectrum clock generator”. When a clock signal having the spectrum properties as indicated by S1 of FIG. 12 is subjected to frequency modulation by the SSCG circuit 102, the clock signal is converted into a signal having the spectrum properties indicated by S2 of FIG. 12, in such a case, the intensity of the undesired radiation is lower than that of a clock signal having the spectrum properties as indicated by S1.
However, if the frequency-modulated clock is used in the analog timing generating circuit 104 in the conventional signal processing circuit, because the level of the offset voltage of a waveform output from the CCD 105 fluctuates in synchronization with the frequency modulation of the clock, even when the same density level is read, the level of the image signal periodically fluctuates along one main-scanning line and therefore both a high-level part and a low-level part appear, which causes a problem.
FIG. 13 is a characteristic diagram that explains the relation between frequency and time and the relation between image level and time during frequency modulation as a measure to reduce the undesired radiation. Although, in general, the CCD driving signal is generated using a reference clock that oscillates highly accurately from 50 ppm to 100 ppm if the frequency modulation is performed as a measure to reduce the undesired radiation, the frequency changes with the elapse of time as shown in the graph on the lower portion of FIG. 13, in which the horizontal axis is the time and the vertical axis is the frequency.
More particularly, the frequency increases and decreases smoothly so that a height increased/decreased from the reference frequency does not exceed a predetermined percentage of the reference frequency. The predetermined percentage is, for example, ±0.5% or ±1.0%. Moreover, the frequency has a regular modulating period. As shown in the graph on the lower portion of FIG. 13, the frequency increases by a predetermined height away from the reference frequency in the positive direction, during which the clock period decreases, and then decreases by a predetermined height along the same characteristic curve in the negative direction, during which the clock period increases. The frequency repeats the modulating cycle and then goes back to the reference frequency. Therefore, the frequency becomes the reference frequency at every half period of modulation.
The graph on the upper portion of FIG. 13 illustrates the fluctuation in the image level according to the modulating period. The horizontal axis is time and the vertical axis is the image level. The image level fluctuates in synchronization with the modulating period. Components of the fluctuation appear as noise. FIG. 13 illustrates the fluctuation in the image level along each line. When these lines gather together, the distribution of the low-level parts and the high-level parts appears as undesired fine lines in a read image. The human eye recognizes these undesired lines as moiré patterns. FIG. 14 is a schematic diagram of an image that is obtained by arranging in the sub-scanning direction lines that are subjected to fluctuation in the image level. In an actual output image, parts having a low image level (peak) are dark and parts having a high image level (pit) are light. Therefore, the line between the parts having the low image level and the line between the parts having the high image level appear as stripes.
Japanese Patent Application Laid-open No. 2008-118366 discloses a technology that solves the problem. In the technology, a voltage signal that is synchronized with the frequency modulation of the clock is extracted from the loop filter circuit of the PLL circuit. An analog signal output from the CCD contains noise overlapped therewith that is synchronized with the frequency modulation of the clock. The voltage signal (analog) is applied in the inverse phase to the analog signal output from the CCD so that the noise (components of fluctuation in the image level) is cancelled out.
However, in the technology disclosed in Japanese Patent Application Laid-open No. 2008-118366, because it is necessary to extract the voltage signal that is synchronized with the frequency modulation of a clock generated by the SSCG circuit is weak (several millivolts) and transmit the voltage signal to the analog output unit of the CCD, the waveform may be deformed due to an influence of the noise so that the noise may not be eliminated clearly.